The present invention relates to storage device including a memory cell having a storage element and a switching element, and particularly relates to a storage device performing recording by a verify control, and a method of recording information.
In an information device such as a computer, a high-density DRAM (Dynamic Random Access Memory) capable of high-speed operation has been widely used. However, in the DRAM, since the manufacture process is complicated in comparison with a logic circuit and a signal processing circuit typically used in an electronic device, there is an issue that the manufacture cost is high. Also, the DRAM is a volatile memory in which information is erased by turning off the power source, and it is necessary to frequently perform a refresh operation.
Thus, nonvolatile memory in which the information is not erased even when turning off the power source, for example, an FeRAM (Ferroelectric Random Access Memory), an MRAM (Magnetoresistive Random Access Memory), and the like have been proposed. In these memories, it is possible to continuously hold the written information for a long time without supplying the electric power, and, also, since it is not necessary to perform the refresh operation, the power consumption may be reduced correspondingly. However, there is an issue that miniaturization is not easy in the FeRAM, and there is an issue that a write current is large in the MRAM (for example, Non-patent Document 1).
Thus, as a memory suitable for speeding up the writing speed of the data, a storage device of a new type as illustrated in FIG. 16 and FIG. 17 has been proposed.
FIG. 16 illustrates a memory cell 100 of the storage device. This memory cell 100 includes a variable resistance element 110 whose cross-sectional structure is illustrated in FIG. 17, and an MOS transistor 120 (switching element). The variable resistance element 110 is formed by stacking an electrode 111, an ion source layer 112, a high resistance layer 113, and an electrode 114. The electrode 111 is electrically connected to a bit line BLR, and the electrode 114 is electrically connected to one terminal of the MOS transistor 120, respectively. The other terminal of the MOS transistor 120 is electrically connected to a bit line BLT, and a gate of the MOS transistor 120 is electrically connected to a word line WL, respectively.
In this storage device, when a voltage is applied to the electrode 114 and the electrode 111 so that a current flows from the ion source layer 112 to the high resistance layer 113, the high resistance layer 113 is changed to have a low resistance, and data is written. On the other hand, when the voltage is applied to the electrode 114 and the electrode 111 so that the current flows from the high resistance layer 113 to the ion source layer 112, the high resistance layer 113 is changed to have a high resistance, and the data is erased.
In such a storage device, in comparison with an existing nonvolatile memory or the like, the memory cell may be composed of a simple structure so that there is no size dependency of the element, and it is possible to obtain a large signal so that there is a characteristic resistant to scaling. Also, there is a great advantage that multi-bit recording, that is, storing data of 2 bits or more in one memory cell is possible by controlling a recording current and a recording voltage (Patent Document 1).    Non-patent Document 1: Nikkei Electronics, 2007.7.16, p. 98    Patent Document 1: Japanese Unexamined Patent Publication No. 2005-235360